Output Prediction Logic: A High-Performance CMOS Design Technique

We present Output Prediction Logic (OPL), a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2X to 3 X over (optimized) conventional static CMOS are demonstrated for a variet), of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudonMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4 X to 5 X over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.